/*!
    \file    change log.txt
    \brief   change log for GD32F3X0 firmware

    \version 2026-01-01, V2.6.0, firmware for GD32F3x0
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/
******************* V2.6.0 2026-01-01 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\Template\GD32EBuilder_project

fix reason:
Add GD32EBuilder_project project.

V2.5.0:
none

V2.6.0:
Add GD32EBuilder_project project.
__________________________________________________________________________________________________________________________
______________________Common______________________________________________________________________________________________
Fix file:
..\Utilities\gd32f350r_eval.c

fix reason:
Add int __io_putchar(int ch) function.

V2.5.0:
none

V2.6.0:
#if defined(__GNUC__) && !defined(__clang__)/* For GNU GCC compiler */
/* retarget the C library printf function to the USART, in Eclipse GCC environment */
int __io_putchar(int ch)
{
    usart_data_transmit(EVAL_COM, (uint8_t) ch );
    while(RESET == usart_flag_get(EVAL_COM, USART_FLAG_TBE));
    return ch;
}
#else
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM, USART_FLAG_TBE));

    return ch;
}
#endif /* defined(__GNUC__) && !defined(__clang__) */
__________________________________________________________________________________________________________________________
______________________Common______________________________________________________________________________________________
Fix file:
..\Examples\all module examples\main.c files

fix reason:
Deleted int __io_putchar(int ch) function.

V2.5.0:
int fputc(int ch, FILE *f);

#ifdef GD_ECLIPSE_GCC
/* retarget the C library printf function to the USART, in Eclipse GCC environment */
int __io_putchar(int ch)
{
    usart_data_transmit(EVAL_COM, (uint8_t) ch );
    while(RESET == usart_flag_get(EVAL_COM, USART_FLAG_TBE));
    return ch;
}
#else
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM, USART_FLAG_TBE));

    return ch;
}
#endif /* GD_ECLIPSE_GCC */

V2.6.0:
none
______________________Common______________________________________________________________________________________________
Fix file:
..\Template\gd322f3x0_libopt.h

fix reason:
Change the declaration location of the tsi.h file.

V2.5.0:
#include "gd32f3x0_tsi.h"

#if (defined(GD32F350) || defined(GD32F355) || defined(GD32F370))
#include "gd32f3x0_cec.h"
#include "gd32f3x0_cmp.h"
#include "gd32f3x0_dac.h"
#endif /* GD32F350, GD32F355 and GD32F370*/

V2.6.0:
#if (defined(GD32F350) || defined(GD32F355) || defined(GD32F370))
#include "gd32f3x0_tsi.h"
#include "gd32f3x0_cec.h"
#include "gd32f3x0_cmp.h"
#include "gd32f3x0_dac.h"
#endif /* GD32F350, GD32F355 and GD32F370*/
__________________________________________________________________________________________________________________________
______________________Common______________________________________________________________________________________________
Fix file:
..\Firmware\CMSIS\CMSIS\GD\GD32F3x0\Source\GCC\Ld\gd32f3x0xx_flash.ld
..\Firmware\CMSIS\CMSIS\GD\GD32F3x0\Source\GCC\newlib\syscalls.c
..\Firmware\CMSIS\CMSIS\GD\GD32F3x0\Source\GCC\startup_gd32f3x0.S

fix reason:
Add GCC support files to adapt to Embedded Builder.

V2.5.0:
none

V2.6.0:
Add GCC files for GD32F3x0 chip.
__________________________________________________________________________________________________________________________
______________________system_gd32f3x0.c___________________________________________________________________________________
Fix file:
..\Firmware\CMSIS\GD\GD32F3x0\Source\system_gd32f3x0.c

fix reason:
Fix MISRA-C 2004 errors.

V2.5.0:
                                    if(0 != __delay){                   \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV8;      \
                                        /* AHB = SYSCLK/8 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV16;     \
                                        /* AHB = SYSCLK/16 */           \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }

    /* if fail */
    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) {
        return;
    }

V2.6.0:
                                    if(0U != (__delay)){                \
                                        /* Insert a software delay */   \
                                        for(i=0U; i< (__delay); i++){   \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0U; i< (__delay); i++){   \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0U; i<(__delay); i++){    \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV8;      \
                                        /* AHB = SYSCLK/8 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0U; i<(__delay); i++){    \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV16;     \
                                        /* AHB = SYSCLK/16 */           \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0U; i<(__delay); i++){    \
                                        }                               \
                                    }

    /* if fail */
    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) {
        while(1){
        }
    }
__________________________________________________________________________________________________________________________
______________________system_gd32f3x0.c___________________________________________________________________________________
Fix file:
..\Firmware\CMSIS\GD\GD32F3x0\Source\system_gd32f3x0.c
fix reason:
The software delay of the cut frequency function has some problems, so the position of the function needs to be adjusted.

V2.5.0:
    _soft_delay_(200);

    RCU_CFG0 &= ~(RCU_CFG0_SCS);
    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
V2.6.0:
    RCU_CFG0 &= ~(RCU_CFG0_SCS);
    _soft_delay_(200);

    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
____________________________________________________________________________________________
______________________RCU_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_rcu.c

fix reason:
The software delay of the cut frequency function has some problems, so the position of the function needs to be adjusted.

V2.5.0:
FlagStatus rcu_flag_get(rcu_flag_enum flag)
{
    if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus rcu_flag_get(rcu_flag_enum flag)
{
    FlagStatus rcu_flag = RESET;

    if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
        rcu_flag = SET;
    } else {
        rcu_flag = RESET;
    }

    return rcu_flag;
}
__________________________________________________________________________________________________________________________
______________________GPIO________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_gpio.c

fix reason:
Fix MISRA-C 2004 14.7 errors.

V2.5.0:
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{
    if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{
    if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{
    FlagStatus retval = RESET;

    if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
        retval = SET;
    } else {
        retval = RESET;
    }

    return retval;
}

FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{
    FlagStatus retval = RESET;

    if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
        retval = SET;
    } else {
        retval = RESET;
    }

    return retval;
}
__________________________________________________________________________________________________________________________
______________________I2C_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_i2c.c

fix reason:
Fix MISRA-C 2004 14.7 errors.

V2.5.0:
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
{
    if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
{
    uint32_t intenable = 0U, flagstatus = 0U, bufie;

    /* check BUFIE */
    bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;

    /* get the interrupt enable bit status */
    intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
    /* get the corresponding flag bit status */
    flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));

    if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) {
        if(intenable && bufie) {
            intenable = 1U;
        } else {
            intenable = 0U;
        }
    }
    if((0U != flagstatus) && (0U != intenable)) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
{
    FlagStatus ret;

    if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) {
        ret = SET;
    } else {
        ret = RESET;
    }

    return ret;
}

FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
{
    uint32_t intenable = 0U, flagstatus = 0U, bufie;
    FlagStatus ret;

    /* check BUFIE */
    bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;

    /* get the interrupt enable bit status */
    intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
    /* get the corresponding flag bit status */
    flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));

    if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) {
        if(intenable && bufie) {
            intenable = 1U;
        } else {
            intenable = 0U;
        }
    }
    if((0U != flagstatus) && (0U != intenable)) {
        ret = SET;
    } else {
        ret = RESET;
    }
    return ret;
}
__________________________________________________________________________________________________________________________
______________________CMP_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_cmp.c

fix reason:
Fix MISRA-C errors in cmp_output_level_get().

V2.5.0:
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{
    if(CMP0 == cmp_periph){
        /* get output level of CMP0 */
        if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) {
            return CMP_OUTPUTLEVEL_HIGH;
        }else{
            return CMP_OUTPUTLEVEL_LOW;
        }
    }else{
        /* get output level of CMP1 */
        if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP1O)) {
            return CMP_OUTPUTLEVEL_HIGH;
        }else{
            return CMP_OUTPUTLEVEL_LOW;
        }
    }
}

V2.6.0:
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{
    uint32_t output_level;

    if(CMP0 == cmp_periph) {
        /* get output level of CMP0 */
        if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) {
            output_level = CMP_OUTPUTLEVEL_HIGH;
        }else {
            output_level = CMP_OUTPUTLEVEL_LOW;
        }
    }else {
        /* get output level of CMP1 */
        if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP1O)) {
            output_level = CMP_OUTPUTLEVEL_HIGH;
        }else{
            output_level = CMP_OUTPUTLEVEL_LOW;
        }
    }
    return output_level;
}
__________________________________________________________________________________________________________________________
______________________SYSCFG_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_syscfg.c

fix reason:
Fixed MISRA 2004 14.7 issue.

V2.5.0:
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
{
    if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus syscfg_cps_rdy_flag_get(void)
{
    if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
{
    FlagStatus retval;
    if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) {
        retval = SET;
    } else {
        retval =  RESET;
    }
    return retval;
}

FlagStatus syscfg_cps_rdy_flag_get(void)
{
    FlagStatus retval;
    if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) {
        retval =  SET;
    } else {
        retval =  RESET;
    }
    return retval;
}
__________________________________________________________________________________________________________________________
______________________TIMER_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_timer.c

fix reason:
gd32f3x0_timer.c file update according to MISRA14.7

V2.5.0:
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
{
    if(RESET != (TIMER_INTF(timer_periph) & flag)) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
{
    uint32_t val;
    val = (TIMER_DMAINTEN(timer_periph) & interrupt);
    if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
{
    FlagStatus timer_flag = RESET;
    
    if(RESET != (TIMER_INTF(timer_periph) & flag)) {
        timer_flag = SET;
    } else {
        timer_flag = RESET;
    }
    
    return timer_flag;
}

FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
{
    FlagStatus timer_interrupt_flag = RESET;
    
    uint32_t val;
    val = (TIMER_DMAINTEN(timer_periph) & interrupt);
    if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) {
        timer_interrupt_flag = SET;
    } else {
        timer_interrupt_flag = RESET;
    }
    
    return timer_interrupt_flag;
}

__________________________________________________________________________________________________________________________
______________________DMA_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_dma.c

fix reason:
Fixed MISRA 2004 14.7 issue.

V2.5.0:
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
{
    uint32_t interrupt_enable = 0U, interrupt_flag = 0U;

    switch(flag) {
    case DMA_INT_FLAG_FTF:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
        break;
    case DMA_INT_FLAG_HTF:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
        break;
    case DMA_INT_FLAG_ERR:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
        break;
    default:
        break;
    }

    if(interrupt_flag && interrupt_enable) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
{
    uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
    FlagStatus reval;

    switch(flag) {
    case DMA_INT_FLAG_FTF:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
        break;
    case DMA_INT_FLAG_HTF:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
        break;
    case DMA_INT_FLAG_ERR:
        interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
        interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
        break;
    default:
        break;
    }

    if(interrupt_flag && interrupt_enable) {
        reval = SET;
    } else {
        reval = RESET;
    }
    return reval;
}
__________________________________________________________________________________________________________________________
______________________EXTI_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_exti.c

fix reason:
Fixed MISRA 2004 14.7 issue.

V2.5.0:
FlagStatus exti_flag_get(exti_line_enum linex)
{
    if(RESET != (EXTI_PD & (uint32_t)linex)) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{
    if(RESET != (EXTI_PD & (uint32_t)linex)) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus exti_flag_get(exti_line_enum linex)
{
     FlagStatus reval;
    if(RESET != (EXTI_PD & (uint32_t)linex)) {
        reval = SET;
    } else {
        reval = RESET;
    }
    return reval;
}

FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{
    FlagStatus reval;
    if(RESET != (EXTI_PD & (uint32_t)linex)) {
        reval = SET;
    } else {
        reval = RESET;
    }
    return reval;
}
__________________________________________________________________________________________________________________________
______________________CEC_________________________________________________________________________________________________
Fix file:
..\Examples\CEC\Intercommunication\gd32f3x0_it.c
..\Examples\CEC\Intercommunication\main.c

fix reason:
Communication failure under high optimization level.

V2.5.0:
extern uint8_t rcvdata[10];
extern __IO uint8_t rcvstatus;
extern uint8_t rcv_inc;
extern uint8_t bytenum;

uint8_t rcvdata[10];
/* sent data pointer */
uint8_t *transdata;
__IO uint8_t rcvstatus = 0U;
__IO uint8_t send_inc = 0U, rcv_inc = 0U;

V2.6.0:
extern volatile uint8_t rcvdata[10];
extern __IO uint8_t rcvstatus;
extern __IO uint8_t rcv_inc;
extern __IO uint8_t bytenum;

volatile uint8_t rcvdata[10];
/* sent data pointer */
uint8_t * volatile transdata;
__IO uint8_t rcvstatus = 0U;
__IO uint8_t send_inc = 0U;
__IO uint8_t rcv_inc = 0U;
__________________________________________________________________________________________________________________________
______________________WWDGT_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_wwdgt.c

fix reason:
Fixed MISRA 2004 14.7 issue.

V2.5.0:
FlagStatus wwdgt_flag_get(void)
{
    if(WWDGT_STAT & WWDGT_STAT_EWIF) {
        return SET;
    }
    return RESET;
}

V2.6.0:
FlagStatus wwdgt_flag_get(void)
{
    FlagStatus temp = RESET;
    if(WWDGT_STAT & WWDGT_STAT_EWIF) {
        temp = SET;
    }
    return temp;
}
__________________________________________________________________________________________________________________________
______________________FWDGT_________________________________________________________________________________________________
Fix file:
..\Examples\FWDGT\FWDGT_key.c

fix reason:
main.c removes fwdgt enable();.

V2.5.0:
    /* after 1.6 seconds to generate a reset */
    fwdgt_enable();

V2.6.0:
none
__________________________________________________________________________________________________________________________
______________________FWDGT_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_fwdgt.c

fix reason:
First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.

V2.5.0:
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if((uint32_t)RESET != flag_status) {
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_value;

    return SUCCESS;
}

ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if((uint32_t)RESET != flag_status) {
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    return SUCCESS;
}

ErrStatus fwdgt_window_value_config(uint16_t window_value)
{
    uint32_t time_index = FWDGT_WND_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_WND */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the WUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
    } while((--time_index > 0U) && (RESET != flag_status));

    if(RESET != flag_status) {
        return ERROR;
    }

    FWDGT_WND = WND_WND(window_value);

    return SUCCESS;
}

ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && (RESET != flag_status));

    if(RESET != flag_status) {
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_div;

    timeout = FWDGT_RLD_TIMEOUT;
    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while((--timeout > 0U) && (RESET != flag_status));

    if(RESET != flag_status) {
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    /* reload the counter */
    FWDGT_CTL = FWDGT_KEY_RELOAD;

    return SUCCESS;
}

FlagStatus fwdgt_flag_get(uint16_t flag)
{
    if(FWDGT_STAT & flag) {
        return SET;
    }
    return RESET;
}

V2.6.0:
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_value;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if((uint32_t)RESET != flag_status) {
        status = ERROR;
    }

    return status;
}

ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_RLD */
    FWDGT_RLD = RLD_RLD(reload_value);

    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if((uint32_t)RESET != flag_status) {
        status = ERROR;
    }

    return status;
}

ErrStatus fwdgt_window_value_config(uint16_t window_value)
{
    uint32_t time_index = FWDGT_WND_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_WND */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the WUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
    } while((--time_index > 0U) && (RESET != flag_status));

    if(RESET != flag_status) {
        status = ERROR;
    } else {
        /* do nothing */
    }

    /* configure FWDGT_WND */
    FWDGT_WND = WND_WND(window_value);

    return status;
}

ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;
    ErrStatus status = SUCCESS;

    /* start the free watchdog timer counter */
    FWDGT_CTL = FWDGT_KEY_ENABLE;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_div;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && (RESET != flag_status));

    if(RESET != flag_status) {
        status = ERROR;
    }

    if(SUCCESS == status) {
        /* configure FWDGT_RLD */
        FWDGT_RLD = RLD_RLD(reload_value);

        /* wait until the RUD flag to be reset */
        timeout = FWDGT_RLD_TIMEOUT;
        do {
            flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
        } while((--timeout > 0U) && (RESET != flag_status));

        if(RESET != flag_status) {
            status = ERROR;
        }
    }

    if(SUCCESS == status) {
        /* reload the counter */
        FWDGT_CTL = FWDGT_KEY_RELOAD;
    }

    return SUCCESS;
}

FlagStatus fwdgt_flag_get(uint16_t flag)
{
    FlagStatus flag_stat us = RESET;
    if(FWDGT_STAT & flag) {
        flag_status = SET;
    }
    return flag_status;
}
__________________________________________________________________________________________________________________________
______________________FMC_________________________________________________________________________________________________
Fix file:
..\Examples\FMC\Erase_program\main.c
..\Examples\FMC\Read_protection\main.c

fix reason:
Before adding flash erase/write and operating OB, perform flag clearing operations first. Increase code redundancy.

V2.5.0:
none

V2.6.0:
    /* clear all pending flags */
    fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);

            fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
__________________________________________________________________________________________________________________________
______________________EXTI________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_misc.c

fix reason:
Modify nvic_irq_enable、nvic_irq_disable functions.

V2.5.0:
void nvic_irq_enable(IRQn_Type nvic_irq,
                     uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;

    /* use the priority group value to get the temp_pre and the temp_sub */
    switch((SCB->AIRCR) & (uint32_t)0x700U) {
    case NVIC_PRIGROUP_PRE0_SUB4:
        temp_pre = 0U;
        temp_sub = 0x4U;
        break;
    case NVIC_PRIGROUP_PRE1_SUB3:
        temp_pre = 1U;
        temp_sub = 0x3U;
        break;
    case NVIC_PRIGROUP_PRE2_SUB2:
        temp_pre = 2U;
        temp_sub = 0x2U;
        break;
    case NVIC_PRIGROUP_PRE3_SUB1:
        temp_pre = 3U;
        temp_sub = 0x1U;
        break;
    case NVIC_PRIGROUP_PRE4_SUB0:
        temp_pre = 4U;
        temp_sub = 0x0U;
        break;
    default:
        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
        temp_pre = 2U;
        temp_sub = 0x2U;
        break;
    }

    /* get the temp_priority to fill the NVIC->IP register */
    temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
    temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
    temp_priority = temp_priority << 0x04U;
    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;

    /* enable the selected IRQ */
    NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
}

void nvic_irq_disable(IRQn_Type nvic_irq)
{
    /* disable the selected IRQ.*/
    NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
}

V2.6.0:
void nvic_irq_enable(IRQn_Type nvic_irq,
                     uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t nvic_prigroup , nvic_priority;

    /* check current priority group */
    switch(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) {
    case NVIC_PRIGROUP_PRE0_SUB4:
    case NVIC_PRIGROUP_PRE1_SUB3:
    case NVIC_PRIGROUP_PRE2_SUB2:
    case NVIC_PRIGROUP_PRE3_SUB1:
    case NVIC_PRIGROUP_PRE4_SUB0:
        break;
    default:
        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
        break;
    }
    
    /* get the priority group value */
    nvic_prigroup = NVIC_GetPriorityGrouping();

    /* encoding the pre-emption, subpriority priority */
    nvic_priority = NVIC_EncodePriority(nvic_prigroup, (uint32_t)nvic_irq_pre_priority, (uint32_t)nvic_irq_sub_priority);
    /* set priority */
    NVIC_SetPriority(nvic_irq, nvic_priority);

    /* enable the selected IRQ */
    NVIC_EnableIRQ(nvic_irq);
}

void nvic_irq_disable(IRQn_Type nvic_irq)
{
    /* disable the selected IRQ */
    NVIC_DisableIRQ(nvic_irq);
}
__________________________________________________________________________________________________________________________
______________________gd32f3x0_crc.c___________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_crc.c

fix reason:
MISRAC 2004 rule 17.4 not fit change: crc_block_data_calculate change.

V2.5.0:
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format)
{
    uint8_t *data8;
    uint16_t *data16;
    uint32_t *data32;
    uint32_t index;

    if(INPUT_FORMAT_WORD == data_format) {
        data32 = (uint32_t *)array;
        for(index = 0U; index < size; index++) {
            REG32(CRC) = data32[index];
        }
    } else if(INPUT_FORMAT_HALFWORD == data_format) {
        data16 = (uint16_t *)array;
        for(index = 0U; index < size; index++) {
            REG16(CRC) = data16[index];
        }
    } else {
        data8 = (uint8_t *)array;
        for(index = 0U; index < size; index++) {
            REG8(CRC) =  data8[index];
        }
    }

    return (CRC_DATA);
}

V2.6.0:
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format)
{
    uint32_t data;
    uint32_t index;

    data = (uint32_t)array;

    if(INPUT_FORMAT_WORD == data_format) {
        for(index = 0U; index < size; index++) {
            REG32(CRC) = *(uint32_t *)data;
            data += 4U;
        }
    } else if(INPUT_FORMAT_HALFWORD == data_format) {
        for(index = 0U; index < size; index++) {
            REG16(CRC) = *(uint16_t *)data;
            data += 2U;
        }
    } else {
        for(index = 0U; index < size; index++) {
            REG8(CRC) =   *(uint8_t *)data;
            data += 1U;
        }
    }

    return (CRC_DATA);
}
__________________________________________________________________________________________________________________________
______________________SPI/I2S_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_spi.c

fix reason:
Fixed MISRA 2004 14.7 issue

V2.5.0:
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
{
    if(SPI_CRC_TX == crc) {
        return ((uint16_t)(SPI_TCRC(spi_periph)));
    } else {
        return ((uint16_t)(SPI_RCRC(spi_periph)));
    }
}

FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{
    if(RESET != (SPI_STAT(spi_periph) & flag)) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
{
    uint32_t reg1 = SPI_STAT(spi_periph);
    uint32_t reg2 = SPI_CTL1(spi_periph);

    switch(interrupt) {
    /* SPI/I2S transmit buffer empty interrupt */
    case SPI_I2S_INT_FLAG_TBE:
        reg1 = reg1 & SPI_STAT_TBE;
        reg2 = reg2 & SPI_CTL1_TBEIE;
        break;
    /* SPI/I2S receive buffer not empty interrupt */
    case SPI_I2S_INT_FLAG_RBNE:
        reg1 = reg1 & SPI_STAT_RBNE;
        reg2 = reg2 & SPI_CTL1_RBNEIE;
        break;
    /* SPI/I2S overrun interrupt */
    case SPI_I2S_INT_FLAG_RXORERR:
        reg1 = reg1 & SPI_STAT_RXORERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI config error interrupt */
    case SPI_INT_FLAG_CONFERR:
        reg1 = reg1 & SPI_STAT_CONFERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI CRC error interrupt */
    case SPI_INT_FLAG_CRCERR:
        reg1 = reg1 & SPI_STAT_CRCERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* I2S underrun error interrupt */
    case I2S_INT_FLAG_TXURERR:
        reg1 = reg1 & SPI_STAT_TXURERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI/I2S format error interrupt */
    case SPI_I2S_INT_FLAG_FERR:
        reg1 = reg1 & SPI_STAT_FERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    default :
        break;
    }
    /*get SPI/I2S interrupt flag status */
    if((0U != reg1) && (0U != reg2)) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
{
    uint16_t val;

    if(SPI_CRC_TX == crc) {
        val = ((uint16_t)(SPI_TCRC(spi_periph)));
    } else {
        val = ((uint16_t)(SPI_RCRC(spi_periph)));
    }
    return val;
}

FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{
    FlagStatus ret;

    if(RESET != (SPI_STAT(spi_periph) & flag)) {
        ret = SET;
    } else {
        ret = RESET;
    }
    return ret;
}

FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
{
    uint32_t reg1 = SPI_STAT(spi_periph);
    uint32_t reg2 = SPI_CTL1(spi_periph);
    FlagStatus ret;

    switch(interrupt) {
    /* SPI/I2S transmit buffer empty interrupt */
    case SPI_I2S_INT_FLAG_TBE:
        reg1 = reg1 & SPI_STAT_TBE;
        reg2 = reg2 & SPI_CTL1_TBEIE;
        break;
    /* SPI/I2S receive buffer not empty interrupt */
    case SPI_I2S_INT_FLAG_RBNE:
        reg1 = reg1 & SPI_STAT_RBNE;
        reg2 = reg2 & SPI_CTL1_RBNEIE;
        break;
    /* SPI/I2S overrun interrupt */
    case SPI_I2S_INT_FLAG_RXORERR:
        reg1 = reg1 & SPI_STAT_RXORERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI config error interrupt */
    case SPI_INT_FLAG_CONFERR:
        reg1 = reg1 & SPI_STAT_CONFERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI CRC error interrupt */
    case SPI_INT_FLAG_CRCERR:
        reg1 = reg1 & SPI_STAT_CRCERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* I2S underrun error interrupt */
    case I2S_INT_FLAG_TXURERR:
        reg1 = reg1 & SPI_STAT_TXURERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    /* SPI/I2S format error interrupt */
    case SPI_I2S_INT_FLAG_FERR:
        reg1 = reg1 & SPI_STAT_FERR;
        reg2 = reg2 & SPI_CTL1_ERRIE;
        break;
    default :
        break;
    }
    /*get SPI/I2S interrupt flag status */
    if((0U != reg1) && (0U != reg2)) {
        ret = SET;
    } else {
        ret = RESET;
    }
    return ret;
}
__________________________________________________________________________________________________________________________
______________________SPI/I2S_______________________________________________________________________________________________
Fix file:
..\Examples\SPI\SPI_master_slave_simplex_dma\main.c

fix reason:
Optimize the timing of SPI hardware NSS pulldown to prevent data from being transmitted incorrectly

V2.5.0:
    /* enable SPI */
    spi_enable(SPI1);
    spi_enable(SPI0);

    /* enable SPI0 NSS output */
    spi_nss_output_enable(SPI0);

V2.6.0:
    /* enable SPI0 NSS output */
    spi_nss_output_enable(SPI0);

    /* enable SPI */
    spi_enable(SPI1);
    spi_enable(SPI0);
__________________________________________________________________________________________________________________________
______________________SPI/I2S_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_spi.c
..\Firmware\GD32F3x0_standard_peripheral\Include\gd32f3x0_spi.h
..\Examples\SPI\I2S_master_transmit_dma\main.c
..\Examples\SPI\I2S_slave_recieve_dma\main.c

fix reason:
The I2S parameter macro was changed from I2S_STD_PHILLIPS to I2S_STD_PHILIPS

V2.5.0:
#define I2S_STD_PHILLIPS                I2SCTL_I2SSTD(0)                        /*!< I2S phillips standard */

    i2s_init(SPI0, I2S_MODE_MASTERTX, I2S_STD_PHILLIPS, I2S_CKPL_HIGH);

    i2s_init(SPI0, I2S_MODE_SLAVERX, I2S_STD_PHILLIPS, I2S_CKPL_HIGH);

V2.6.0:
#define I2S_STD_PHILIPS                I2SCTL_I2SSTD(0)                        /*!< I2S philips standard */

    i2s_init(SPI0, I2S_MODE_MASTERTX, I2S_STD_PHILIPS, I2S_CKPL_HIGH);

    i2s_init(SPI0, I2S_MODE_SLAVERX, I2S_STD_PHILIPS, I2S_CKPL_HIGH);
__________________________________________________________________________________________________________________________
______________________SPI/I2S_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Include\gd32f3x0_spi.h
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_spi.c

fix reason:
Delete the bit2 of IO23_DRV of the SPI_QCTL register and the associated function.

V2.5.0:
#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */

/* enable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_enable(uint32_t spi_periph);
/* disable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_disable(uint32_t spi_periph);

/*!
    \brief      enable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output
    \param[in]  spi_periph: SPI1
    \param[out] none
    \retval     none
*/
void spi_quad_io23_output_enable(uint32_t spi_periph)
{
    SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
}

/*!
   \brief      disable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output
   \param[in]  spi_periph: SPI1
   \param[out] none
   \retval     none
*/
void spi_quad_io23_output_disable(uint32_t spi_periph)
{
    SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
}

V2.6.0:
none
__________________________________________________________________________________________________________________________
______________________PMU_________________________________________________________________________________________________
Fix file:
..Examples\PMU\Deepsleep_wakeup_exti\main.c
..Examples\PMU\Deepsleep_wakeup_RTC\main.c
..Examples\PMU\Standby_wakeup_RTC\main.c
..Examples\PMU\Standby_wakeup_pin\main.c
fix reason:
PMU consistency modification: Add frequency switching logic to Example.

V2.5.0:
none

V2.6.0:
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

        /* The following is to prevent Vcore fluctuations caused by frequency switching.
        It is strongly recommended to include it to avoid issues caused by self-removal. */
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV2);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV4);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV8);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV16);
        _soft_delay_(0x50);
__________________________________________________________________________________________________________________________
______________________PMU_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_pmu.c
fix reason:
PMU consistency modification: The pmu_to_sleepmode interface requires one SEV instruction and two WFE instructions to sleep in WFE mode.

V2.5.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __WFE();
    }
}

V2.6.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __SEV();
        __WFE();
        __WFE();
    }
}
__________________________________________________________________________________________________________________________
______________________USART_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_usart.c

fix reason:
Modify MISARC-2004 issue.

V2.5.0:
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{
    if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) {
        return SET;
    } else {
        return RESET;
    }
}

FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag)
{
    uint32_t intenable = 0U, flagstatus = 0U;
    /* get the interrupt enable bit status */
    intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
    /* get the corresponding flag bit status */
    flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));

    if(flagstatus && intenable) {
        return SET;
    } else {
        return RESET;
    }
}

V2.6.0:
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{
    FlagStatus ret = RESET;

    if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) {
        ret = SET;
    } else {
        ret = RESET;
    }
    return ret;
}

FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag)
{
    FlagStatus ret = RESET;
    uint32_t intenable = 0U, flagstatus = 0U;
    /* get the interrupt enable bit status */
    intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
    /* get the corresponding flag bit status */
    flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));

    if(flagstatus && intenable) {
        ret = SET;
    } else {
        ret = RESET;
    }
    return ret;
}
__________________________________________________________________________________________________________________________
______________________USART_______________________________________________________________________________________________
Fix file:
..\Examples\USART\Half_duplex_transmitter&receiver\main.c
fix reason:
Modify the pin configuration of half-duplex communication.

V2.5.0:
    /* configure USART0 Tx as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);

    /* configure USART1 Tx as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);

V2.6.0:
    /* configure USART0 Tx as alternate function open-drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_9);

    /* configure USART1 Tx as alternate function open-drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Examples\USBFS\all examples

fix reason: 
Add EB projects, correct project compilation errors, and adjust serial port redirection error issues.

V2.5.0:
none

V2.6.0:
Add EB projects, correct project compilation errors, and adjust serial port redirection error issues.
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Examples\USBFS\USB_Device\in_application_program_hid\src\flash_operation.c

fix reason: 
Solve the problem of failure when writing large files first and then small files in flash.

V2.5.0:
   for(idx = 0U; idx < len; idx += 2) {
        status = fmc_halfword_program(addr, *(uint32_t *)(data + idx));

V2.6.0:
    for(idx = 0U; idx < len; idx += 2) {

        if(*(uint16_t *)(data + idx) == 0xFFFF) {
            status = FMC_READY;
        } else {
            status = fmc_halfword_program(addr, *(uint32_t *)(data + idx));
        }
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Examples\USBFS\USB_Device\in_application_program_hid\src\flash_operation.c

fix reason: 
Fix the issue of failed BIN file writing for integer multiples encountered during IAP firmware upgrade.

V2.5.0:
    /* data received are word multiple */
    for(idx = 0U; idx < len; idx += 2) {

        if(*(uint16_t *)(data + idx) == 0xFFFF) {
            status = FMC_READY;
        } else {
            status = fmc_halfword_program(addr, *(uint16_t *)(data + idx));
        }

        if(FMC_READY == status){
            addr += 2U;
        }else{
            while(1){
            }
        }
    }

V2.6.0:
static uint32_t packet_count = 0;

    if(0U == (file_length % TRANSFER_SIZE)){
        packet_count = (uint32_t)(file_length / TRANSFER_SIZE);
    }else{
        packet_count = (uint32_t)(file_length / TRANSFER_SIZE + 1U);
    }

    packet_count--;

    packet_count--;

    /* data received are word multiple */
    for(idx = 0U; idx < len; idx += 2) {
        status = fmc_halfword_program(addr, *(uint16_t *)(data + idx));
        if(FMC_READY == status){
            addr += 2U;
        } else {
            if(0U == packet_count) {
                addr += 2U;
                fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
                status = FMC_READY;
            } else {
            }
        }
    }
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_usbfs_library\driver\core\Source\usb_core.c

fix reason: 
Modify the firmware library and pass the self-powered CVTest.

V2.5.0:
none

V2.6.0:
    /* configure power management */
    udev->dev.pm.power_mode = (udev->dev.desc->config_desc[7] & BIT(6)) >> 6;
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Examples\USBFS\USB_Device\dev_firmware_update\src\inter_flash_if.c

fix reason: 
Modify the function name to avoid compilation errors in higher versions of the compiler.

V2.5.0:
static fmc_state_enum fmc_state_get(void);
static fmc_state_enum fmc_ready_wait(uint32_t timeout);

    status = fmc_ready_wait(FMC_TIMEOUT_COUNT);

    status = fmc_ready_wait(FMC_TIMEOUT_COUNT);

        status = fmc_ready_wait(FMC_TIMEOUT_COUNT);

static fmc_state_enum fmc_state_get(void)

static fmc_state_enum fmc_ready_wait(uint32_t timeout)
{
    fmc_state_enum fmc_state = FMC_BUSY;

    /* wait for FMC ready */
    do {
        /* get FMC state */
        fmc_state = fmc_state_get();
        timeout--;
    } while((FMC_BUSY == fmc_state) && (0x00U != timeout));

    if(FMC_BUSY == fmc_state) {
        fmc_state = FMC_TOERR;
    }
    /* return the FMC state */
    return fmc_state;
}

V2.6.0:
static fmc_state_enum inter_flash_state_get(void);
static fmc_state_enum inter_flash_ready_wait(uint32_t timeout);

    status = inter_flash_ready_wait(FMC_TIMEOUT_COUNT);

    status = inter_flash_ready_wait(FMC_TIMEOUT_COUNT);

        status = inter_flash_ready_wait(FMC_TIMEOUT_COUNT);

static fmc_state_enum inter_flash_state_get(void)

static fmc_state_enum inter_flash_ready_wait(uint32_t timeout)
{
    fmc_state_enum fmc_state = FMC_BUSY;

    /* wait for FMC ready */
    do {
        /* get FMC state */
        fmc_state = inter_flash_state_get();
        timeout--;
    } while((FMC_BUSY == fmc_state) && (0x00U != timeout));

    if(FMC_BUSY == fmc_state) {
        fmc_state = FMC_TOERR;
    }
    /* return the FMC state */
    return fmc_state;
}
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3x0_usbfs_library\driver\Source\drv_usb_dev.c

fix reason: 
Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.
Shift the value of enum_speed after obtaining the ES bit field.

V2.5.0:
    uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;

V2.6.0:
    uint32_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1);
__________________________________________________________________________________________________________________________
______________________USBFS_______________________________________________________________________________________________
Fix file:
..\Examples\USBFS\USB_Device\all demos\system_gd32f3x0.c
..\Examples\USBFS\USB_Host\all demos\system_gd32f3x0.c
fix reason: 
Added the RCU frequency cutting function to the system clock configuration in the system clock configuration file.
V2.5.0:
none
V2.6.0:
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY_4(__delay)   do{                                     \
                                    volatile uint32_t i, reg;           \
                                    if(0 != __delay){                   \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV8;      \
                                        /* AHB = SYSCLK/8 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV16;     \
                                        /* AHB = SYSCLK/16 */           \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)

/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }

    if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLL)){
        RCU_MODIFY_4(0x50);
    }

    RCU_CFG0 &= ~(RCU_CFG0_SCS);
    _soft_delay_(200);

    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
__________________________________________________________________________________________________________________________
******************* V1.2.0 2023-09-11 ******************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file: all file


fix reason:
add  (GD32F355)  and (GD32F370))
V2.3.0:
#if (defined(GD32F350) || defined(GD32F330))
V2.4.0:
#if (defined(GD32F350) || defined(GD32F355) || defined(GD32F370))
__________________________________________________________________________________________________________________________

________________________ FMC _______________________________________________________________________________________

__________________________________________________________________________________________________________________________

______________________PMU_____________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________RCU_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________CTC____________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________EXTI____________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________GPIO________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________CRC________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________DMA_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________DBG________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________ADC_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________DAC______________________________________________________________________________________________
Fix file:
GD32F3x0_Firmware_Library\Firmware\GD32F3x0_standard_peripheral\Source\gd32f3x0_cmp.c
GD32F3x0_Firmware_Library\Firmware\GD32F3x0_standard_peripheral\Include\gd32f3x0_cmp.h
fix reason:
"BKIN" is changed to "BRKIN" to be consistent with the datasheet and User Manual (UM).
V2.3.0:
#define CMP_OUTPUT_TIMER0_BKIN                   CS_CMPXOSEL(1)                 /*!< CMP output TIMER0 break input */
V2.4.0:
#define CMP_OUTPUT_TIMER0_BRKIN                  CS_CMPXOSEL(1)                 /*!< CMP output TIMER0 break input */

__________________________________________________________________________________________________________________________

______________________CMP_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________WDGT________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________RTC_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________TIMER_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________IFRP_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________USART_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________I2C_____________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________SPI/I2S_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________HDMI-CEC_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________TSI_________________________________________________________________________________________________


__________________________________________________________________________________________________________________________

______________________USBFS______________________________________________________________________________________________
Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Include\usb_iap_core.h
fix reason: 
Changing IAP commands due to IAP protocol modification
V3.5.0:
/* special commands with download request */
#define IAP_OPTION_BYTE1                    0x01U
#define IAP_ERASE                           0x02U
#define IAP_DNLOAD                          0x03U
#define IAP_LEAVE                           0x04U
#define IAP_GETBIN_ADDRESS                  0x05U
#define IAP_OPTION_BYTE2                    0x06U
V3.6.0:
/* special commands with download request */
#define IAP_READ_OPTION_BYTE                0x01U                                  /*!< read option byte request */
#define IAP_ERASE                           0x02U                                  /*!< erase request */
#define IAP_DOWNLOAD                        0x03U                                  /*!< download request */
#define IAP_LEAVE                           0x04U                                  /*!< leave request */
#define IAP_GETBIN_ADDRESS                  0x05U                                  /*!< get bin address request */
#define IAP_WRITE_OPTION_BYTE               0x06U                                  /*!< write option byte request */
#define IAP_UPLOAD                          0x07U                                  /*!< upload request */
#define IAP_CHECK_RDP                       0x08U                                  /*!< check rdp state request */

#define OPERATION_SUCCESS                   0x02U                                  /*!< operation success status */
#define OPERATION_FAIL                      0x5FU                                  /*!< operation fail status */
#define LEAVE_FINISH                        0x04U                                  /*!< leave finish status */
#define OB_WRITE_SUCCESS                    0x03U                                  /*!< OB write success status */
#define IS_RDP_MODE                         0xBBU                                  /*!< MCU RDP status */
#define IS_NORMAL_MODE                      0xA5U                                  /*!< MCU normal status */

#define IAP_HOST_ID                         0x01U                                  /*!< IAP host ID */
#define IAP_DEVICE_ID                       0x02U                                  /*!< IAP device ID */


Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP DATA OUT function due to IAP protocol modification
V2.3.0:
/*!
    \brief      handle data out stage
    \param[in]  udev: pointer to USB device instance
    \param[in]  ep_num: endpoint identifier
    \param[out] none
    \retval     none
*/
static uint8_t iap_data_out (usb_dev *udev ,uint8_t ep_num)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if (0x01U == iap->report_buf[0]) {
        switch (iap->report_buf[1]) {
        case IAP_DNLOAD:
            iap_req_dnload(udev);
            break;

        case IAP_ERASE:
            iap_req_erase(udev);
            break;

        case IAP_OPTION_BYTE1:
            iap_req_optionbyte(udev, 0x01U);
            break;

        case IAP_LEAVE:
            iap_req_leave(udev);
            break;

        case IAP_GETBIN_ADDRESS:
            iap_address_send(udev);
            break;

        case IAP_OPTION_BYTE2:
            iap_req_optionbyte(udev, 0x02U);
            break;

        default:
            break;
        }
    }

    usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET);

    return USBD_OK;
}
V2.4.0:
/*!
    \brief      handle data OUT stage
    \param[in]  udev: pointer to USB device instance
    \param[in]  ep_num: endpoint number
    \param[out] none
    \retval     USB device operation status
*/
static uint8_t iap_data_out(usb_dev *udev, uint8_t ep_num)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if(IAP_HOST_ID == iap->report_buf[0]) {
        switch(iap->report_buf[1]) {
        case IAP_DOWNLOAD:
            iap_req_download(udev);
            break;

        case IAP_ERASE:
            iap_req_erase(udev);
            break;

        case IAP_READ_OPTION_BYTE:
            iap_req_read_optionbyte(udev);
            break;

        case IAP_LEAVE:
            iap_req_leave(udev);
            break;

        case IAP_GETBIN_ADDRESS:
            iap_address_send(udev);
            break;

        case IAP_WRITE_OPTION_BYTE:
            iap_req_write_optionbyte(udev);
            break;

        case IAP_UPLOAD:
            iap_req_upload(udev);
            break;

        case IAP_CHECK_RDP:
            iap_check_rdp(udev);
            break;

        default:
            break;
        }
    }

    usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET);

    return USBD_OK;
}

Fix file:
\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP download request function due to IAP protocol modification
V3.5.0:
/*!
    \brief      handle the IAP_DNLOAD request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_dnload(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if (0U != iap->transfer_times) {
        if (1U == iap->transfer_times) {
            if (0U == iap->lps) {
                iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE);
            } else {
                iap_data_write(&iap->report_buf[2], iap->base_address, iap->file_length % TRANSFER_SIZE);
                iap->lps = 0U;
            }

            iap->dev_status[0] = 0x02U;
            iap->dev_status[1] = 0x02U;
            iap_report_send (udev, iap->dev_status, IAP_IN_PACKET);
        } else {
            iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE);

            iap->base_address += TRANSFER_SIZE;
        }

        iap->transfer_times--;
    }
}
V3.6.0:
/*!
    \brief      handle the IAP_DOWNLOAD request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_download(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->dev_status[0] = IAP_DEVICE_ID;

    /* get the target address to download */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    /* program the target address */
    if(FMC_READY == iap_data_write(&iap->report_buf[6], iap->base_address, TRANSFER_SIZE)) {
        iap->dev_status[1] = OPERATION_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    iap_report_send(udev, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Adding IAP write option byte request function due to IAP protocol modification
V2.3.0:
none
V2.4.0:
/*!
    \brief      handle the IAP_WRITE_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_write_optionbyte(usb_dev *udev)
{
    uint32_t option_byte_addr = 0U;
    uint16_t option_byte_size = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get option byte address address */
    option_byte_addr  = iap->report_buf[2];
    option_byte_addr |= (uint32_t)iap->report_buf[3] << 8;
    option_byte_addr |= (uint32_t)iap->report_buf[4] << 16;
    option_byte_addr |= (uint32_t)iap->report_buf[5] << 24;

    /* get option byte address size */
    if(OPT_BYTE_ADDR == option_byte_addr) {
        option_byte_size = OPT_BYTE_SIZE;
    }

    iap->dev_status[0] = IAP_DEVICE_ID;

    /* write option byte address data */
    if(FMC_READY == option_byte_write(option_byte_addr, &iap->report_buf[6], option_byte_size)) {
        iap->dev_status[1] = OB_WRITE_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    iap_report_send(udev, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP erase flash request function due to IAP protocol modification
V2.3.0:
/*!
    \brief      handle the IAP_ERASE request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_erase(usb_dev *udev)
{
    uint32_t addr = 0U;

    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to erase */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= iap->report_buf[3] << 8U;
    iap->base_address |= iap->report_buf[4] << 16U;
    iap->base_address |= iap->report_buf[5] << 24U;

    /* get file length */
    iap->file_length = iap->report_buf[7];
    iap->file_length |= iap->report_buf[8] << 8U;
    iap->file_length |= iap->report_buf[9] << 16U;
    iap->file_length |= iap->report_buf[10] << 24U;

    iap->lps = iap->file_length % TRANSFER_SIZE;
    if (0U == iap->lps) {
        iap->transfer_times = iap->file_length / TRANSFER_SIZE;
    } else {
        iap->transfer_times = iap->file_length / TRANSFER_SIZE + 1U;
    }

    /* check if the address is in protected area */
    if (IS_PROTECTED_AREA(iap->base_address)) {
        return;
    }

    addr = iap->base_address;

    /* unlock the flash program erase controller */
    fmc_unlock();

    flash_erase(addr, iap->file_length, iap->report_buf);

    fmc_lock();

    iap->dev_status[0] = 0x02U;
    iap->dev_status[1] = 0x01U;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);
}
V2.4.0:
/*!
    \brief      handle the IAP_ERASE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_erase(usb_dev *udev)
{
    uint32_t addr = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to erase */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    /* get file length */
    iap->file_length = iap->report_buf[6];
    iap->file_length |= (uint32_t)iap->report_buf[7] << 8;
    iap->file_length |= (uint32_t)iap->report_buf[8] << 16;
    iap->file_length |= (uint32_t)iap->report_buf[9] << 24;

    /* check if the address is in protected area */
    if(IS_PROTECTED_AREA(iap->base_address)) {
        return;
    }

    addr = iap->base_address;
    iap->dev_status[0] = IAP_DEVICE_ID;

    if(FMC_READY == flash_erase(addr, iap->file_length)) {
        iap->dev_status[1] = OPERATION_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP read option byte request function due to IAP protocol modification
V2.3.0:
/*!
    \brief      handle the IAP_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[in]  option_num: number of option byte
    \param[out] none
    \retval     none
*/
static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num)
{
    uint8_t i = 0U;
    uint32_t address = 0U;

    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->option_byte[0] = 0x02U;

    if (0x01U == option_num) {
        address = OPT_BYTE_ADDR1;
#ifdef OPT_BYTE_ADDR2
    } else if (0x02U == option_num) {
        address = OPT_BYTE_ADDR2;
#endif
    } else {
        return;
    }

    for (i = 1U; i < 17U; i++) {
        iap->option_byte[i] = *(uint8_t *)address;
        address++;
    }

    iap_report_send (udev, iap->option_byte, IAP_IN_PACKET);
}
V2.4.0:
/*!
    \brief      handle the IAP_READ_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_read_optionbyte(usb_dev *udev)
{
    uint8_t i = 0U;
    uint32_t option_size = 0U, temp = 0U, option_address = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* read option address address */
    option_address = iap->report_buf[2] + (iap->report_buf[3] << 8) + (iap->report_buf[4] << 16) + (iap->report_buf[5] << 24);

    iap->option_byte[0] = IAP_DEVICE_ID;

    if(OPT_BYTE_ADDR == option_address) {
        option_size = OPT_BYTE_SIZE;
    }

    /* read option address content */
    for(i = 0U; i < (option_size / 4U); i++) {
        temp =  *(uint32_t *)option_address;
        iap->option_byte[4 * i + 5] = temp >> 24;
        iap->option_byte[4 * i + 4] = temp >> 16;
        iap->option_byte[4 * i + 3] = temp >> 8;
        iap->option_byte[4 * i + 2] = temp;
        option_address = option_address + 4U;
    }
    iap->option_byte[1] = OPERATION_SUCCESS;

    iap_report_send(udev, iap->option_byte, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing leave IAP mode request function due to IAP protocol modification
V2.3.0:
/*!
    \brief      handle the IAP_LEAVE request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_leave(usb_dev *udev)
{
    /* lock the internal flash */
    fmc_lock();

    /* generate system reset to allow jumping to the user code */
    NVIC_SystemReset();
}
V2.4.0:
/*!
    \brief      handle the IAP_LEAVE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_leave(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to jump */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    iap->dev_status[0] = IAP_DEVICE_ID;
    iap->dev_status[1] = LEAVE_FINISH;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);

    usbd_disconnect(udev);

    /* reset register */
    register_reset();

    /* jump to target */
    jump_to_execute(iap->base_address);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP upload request function due to IAP protocol modification
V2.3.0:
none
V2.4.0:
/*!
    \brief      handle the IAP_UPLOAD request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_upload(usb_dev *udev)
{
    uint16_t packet_valid_length = 0U, i= 0U;
    uint32_t bin_flash_addr = APP_LOADED_ADDR;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->bin_addr[0] = IAP_DEVICE_ID;

    /* get target flash address */
    bin_flash_addr  = iap->report_buf[2];
    bin_flash_addr |= (uint32_t)iap->report_buf[3] << 8;
    bin_flash_addr |= (uint32_t)iap->report_buf[4] << 16;
    bin_flash_addr |= (uint32_t)iap->report_buf[5] << 24;

    /* get current packet valid length */
    packet_valid_length = iap->report_buf[6];
    packet_valid_length |= iap->report_buf[7] << 8;

    /* get target flash address content */
    for(i = 0U; i < packet_valid_length; i++) {
        iap->bin_addr[i + 1] = REG8(bin_flash_addr + i);
    }

    iap_report_send(udev, iap->bin_addr, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Adding IAP check read protected request function due to IAP protocol modification
V2.3.0:
none
V2.4.0:
/*!
    \brief      handle the IAP_CHECK_RDP request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_check_rdp(usb_dev *udev)
{
    uint8_t mode = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* check whether the SPC bit of FMC module is normal state */
    if(0xA5U != REG8(OPT_BYTE_ADDR)) {
        mode = IS_RDP_MODE;
    } else {
        mode = IS_NORMAL_MODE;
    }

    iap->bin_addr[0] = IAP_DEVICE_ID;
    iap->bin_addr[1] = mode;

    iap_report_send(udev, iap->bin_addr, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F3X0_usbd_library\device\class\msc\Include\usbd_msc_scsi.h
fix reason: 
The statement here can be removed
V2.3.0:
extern const uint8_t msc_page00_inquiry_data[];
extern const uint8_t msc_mode_sense6_data[];
extern const uint8_t msc_mode_sense10_data[];
V2.4.0:
none

Fix file:
..\Firmware\GD32F3X0_usbd_library\usbd\Include\usbd_lld_regs.h
fix reason: 
MCU register operation is a read-modify-write-back process, and RX_ST and TX_ST in the
USBD_EPxCS register are write 0 valid, write 1 invalid bits, so that if RX_ST and TX_ST
are 0 when reading out the USBD_EPxCS register, and the hardware will set RT_ST or TX_ST
when rewriting the value of the register, then the write-back process This interrupt has
not yet been processed, resulting in lost interrupt processing.
V2.3.0:
#define USBD_EP_TX_STAT_SET(ep, stat) do {\
    USBD_EPxCS(ep) = (USBD_EPxCS(ep) & (uint16_t)EPTX_DTGMASK) ^ (stat); \
} while(0)

#define USBD_EP_RX_STAT_SET(ep, stat) do {\
    USBD_EPxCS(ep) = (USBD_EPxCS(ep) & (uint16_t)EPRX_DTGMASK) ^ (stat); \
} while(0)

/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */

#define USBD_EP_TX_ST_CLEAR(ep) do {\
    USBD_EPxCS(ep) &= ~EPxCS_TX_ST & (uint16_t)EPCS_MASK; \
} while(0)

#define USBD_EP_RX_ST_CLEAR(ep) do {\
    USBD_EPxCS(ep) &= ~EPxCS_RX_ST & (uint16_t)EPCS_MASK; \
} while(0)

/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */

#define USBD_TX_DTG_TOGGLE(ep) do {\
    USBD_EPxCS(ep) = EPxCS_TX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
} while(0)

#define USBD_RX_DTG_TOGGLE(ep) do {\
    USBD_EPxCS(ep) = EPxCS_RX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
} while(0)

/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */

#define USBD_TX_DTG_CLEAR(ep) do {\
    if ((USBD_EPxCS(ep_num) & EPxCS_TX_DTG) != 0U) {\
        USBD_TX_DTG_TOGGLE(ep);\
    } \
} while(0)

#define USBD_RX_DTG_CLEAR(ep) do {\
    if ((USBD_EPxCS(ep_num) & EPxCS_RX_DTG) != 0U) {\
        USBD_RX_DTG_TOGGLE(ep);\
    } \
} while(0)

#define USBD_EP_DBL_BUF_SET(ep) (USBD_EPxCS(ep) = (USBD_EPxCS(ep) | EPxCS_KCTL) & EPCS_MASK)
V2.4.0:
#define USBD_EP_TX_STAT_SET(ep, stat) do { \
    uint16_t regval; \
    regval = (USBD_EPxCS(ep) & (uint16_t)EPTX_DTGMASK) ^ (stat); \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST | EPxCS_TX_ST; \
} while(0)

#define USBD_EP_RX_STAT_SET(ep, stat) do { \
    uint16_t regval; \
    regval = (USBD_EPxCS(ep) & (uint16_t)EPRX_DTGMASK) ^ (stat); \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST | EPxCS_TX_ST; \
} while(0)

/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */

#define USBD_EP_TX_ST_CLEAR(ep) do { \
    uint16_t regval; \
    regval = USBD_EPxCS(ep) & (~EPxCS_TX_ST & (uint16_t)EPCS_MASK); \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST; \
} while(0)

#define USBD_EP_RX_ST_CLEAR(ep) do { \
    uint16_t regval; \
    regval = USBD_EPxCS(ep) & (~EPxCS_RX_ST & (uint16_t)EPCS_MASK); \
    USBD_EPxCS(ep) = regval | EPxCS_TX_ST; \
} while(0)

/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */

#define USBD_TX_DTG_TOGGLE(ep) do { \
    uint16_t regval; \
    regval = EPxCS_TX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST | EPxCS_TX_ST; \
} while(0)

#define USBD_RX_DTG_TOGGLE(ep) do { \
    uint16_t regval; \
    regval = EPxCS_RX_DTG | (USBD_EPxCS(ep) & EPCS_MASK); \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST | EPxCS_TX_ST; \
} while(0)

/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */

#define USBD_TX_DTG_CLEAR(ep) do { \
    if(0U != (USBD_EPxCS(ep) & EPxCS_TX_DTG)) { \
        USBD_TX_DTG_TOGGLE(ep); \
    } \
} while(0)

#define USBD_RX_DTG_CLEAR(ep) do { \
    if(0U != (USBD_EPxCS(ep) & EPxCS_RX_DTG)) { \
        USBD_RX_DTG_TOGGLE(ep); \
    } \
} while(0)

#define USBD_EP_DBL_BUF_SET(ep) do { \
    uint16_t regval; \
    regval = (USBD_EPxCS(ep) | EPxCS_KCTL) & EPCS_MASK; \
    USBD_EPxCS(ep) = regval | EPxCS_RX_ST | EPxCS_TX_ST; \
} while(0)


Fix file:
..\Firmware\GD32F3X0_usbd_library\usbd\Source\usbd_lld_core.c
fix reason: 
RBCNT register configuration error
V2.3.0:
btable_ep[ep_num].rx_count = ((uint16_t)((uint16_t)transc->max_len << 5) - 1U) | 0x8000U;
V2.4.0:
if (transc->max_len & 0x1FU) {
	btable_ep[ep_num].rx_count = (((uint16_t)transc->max_len >> 5) << 10) | 0x8000U; 
} else {
	btable_ep[ep_num].rx_count = ((((uint16_t)transc->max_len >> 5) - 1U) << 10) | 0x8000U; 
}

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